1. Technical Field
This disclosure relates to the execution of instructions in a multi-threaded computing environment, and, more specifically, to the use of instruction miss buffers in such an environment.
2. Description of the Related Art
When executing a computer program, a microprocessor may experience periods of delay in which no instructions are executed. For example, a program's execution may be delayed (stalled) when one or more program instructions are not present in an instruction cache. Although program execution may be resumed once the one or more instructions are fetched and become available, overall execution time may have been increased due to one or more periods of stalling that occurred.
In a microprocessor that implements chip level multi-threading, multiple software threads are concurrently active, and execution of instructions may be interleaved among the active threads. Accordingly, in a multi-threaded processor, multiple threads may face the possibility of one or more program instructions not being present in an instruction cache, and the possibility of stalling.